maste
This commit is contained in:
Wang Xuejin
@@ -1,2 +1,11 @@
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# palladium_z2_demo
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# RISC-V Demo for Palladium Z2
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## 目录结构
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riscv_demo/
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├── design/
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│ └── top.v # RISC-V 顶层模块
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├── testbench/
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│ └── testbench.v # 测试激励
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└── scripts/
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└── run_all.tcl # Palladium Z2 脚本
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@@ -0,0 +1,13 @@
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`timescale 1ns/1ps
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module top (
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input clk,
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input reset_n,
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output [31:0] pc_out
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);
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reg [31:0] pc;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) pc <= 0;
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else pc <= pc + 4;
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end
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assign pc_out = pc;
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endmodule
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@@ -0,0 +1,41 @@
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# run_all.tcl - Palladium Z2 Demo Script
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puts "INFO: Starting Palladium Z2 simulation..."
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set DESIGN_NAME "top"
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set WORK_DIR "./work"
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file mkdir $WORK_DIR
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cd $WORK_DIR
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# 加载设计（示例，实际需替换为你的编译命令）
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puts "INFO: Loading design into Palladium Z2..."
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if {[catch {load_design -format verilog -top $DESIGN_NAME} err]} {
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puts "ERROR: Failed to load design: $err"
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exit 1
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}
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# 配置波形数据库
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puts "INFO: Setting up waveform database..."
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database -open waves -shm
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probe -create -all -depth all -database waves
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# 运行仿真
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puts "INFO: Running simulation for 1000 cycles..."
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run 1000
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# 调试信息
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if {[task_exists show_cpu_pc]} {
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show_cpu_pc
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} else {
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puts "WARNING: show_cpu_pc task not found"
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}
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# 保存波形
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if {[file exists waves.shm]} {
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puts "INFO: Saving waveform traces..."
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trace -name basic -database waves -add *
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trace -save -database waves ./wave_debug.trn
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} else {
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puts "WARNING: No waveform database found"
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}
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puts "INFO: Simulation completed successfully."
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exit 0
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@@ -0,0 +1,63 @@
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## xeDebug starts at 09/22/2025 14:48:07, PID: 100527
|
||||
REMOTEHOST=172.16.10.16
|
||||
BLT_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/ui/blt
|
||||
XDG_SESSION_ID=21345
|
||||
HOSTNAME=scmp23
|
||||
S3_ROOT=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin/64bit
|
||||
HOST=scmp23
|
||||
TERM=xterm
|
||||
SHELL=/bin/csh
|
||||
AXIS_HOME=/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86
|
||||
SSH_CLIENT=172.16.10.16 53482 22
|
||||
QTHOME=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86
|
||||
TIX_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/ui/tix
|
||||
TK_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/ui/tk
|
||||
USERPATH=/edatools/cadence/XCELIUM/XCELIUM23.09.001/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/inca/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools/cdsgcc/gcc/bin:/edatools/cadence/IXCOM/IXCOM23.03.005/bin:/edatools/cadence/WXE/WXE23.03.s005/share/vxe/gift/misc:/edatools/cadence/WXE/WXE23.03.s005/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/usr/local/sbin:/usr/sbin
|
||||
QTDIR=/usr/lib64/qt-3.3
|
||||
QTINC=/usr/lib64/qt-3.3/include
|
||||
SSH_TTY=/dev/pts/0
|
||||
QT_GRAPHICSSYSTEM_CHECKED=1
|
||||
GROUP=domain users
|
||||
USER=xuejin.wang
|
||||
LD_LIBRARY_PATH=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/lib/64bit:/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86/lib/64bit:/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86/lib/64bit:/usr/lib64:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools/systemc/lib/64bit/gnu:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/lib/64bit:/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86/lib/64bit:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/lib/64bit
|
||||
LS_COLORS=rs=0:di=01;34:ln=01;36:mh=00:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:mi=01;05;37;41:su=37;41:sg=30;43:ca=30;41:tw=30;42:ow=34;42:st=37;44:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arc=01;31:*.arj=01;31:*.taz=01;31:*.lha=01;31:*.lz4=01;31:*.lzh=01;31:*.lzma=01;31:*.tlz=01;31:*.txz=01;31:*.tzo=01;31:*.t7z=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.dz=01;31:*.gz=01;31:*.lrz=01;31:*.lz=01;31:*.lzo=01;31:*.xz=01;31:*.bz2=01;31:*.bz=01;31:*.tbz=01;31:*.tbz2=01;31:*.tz=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.war=01;31:*.ear=01;31:*.sar=01;31:*.rar=01;31:*.alz=01;31:*.ace=01;31:*.zoo=01;31:*.cpio=01;31:*.7z=01;31:*.rz=01;31:*.cab=01;31:*.jpg=01;35:*.jpeg=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.png=01;35:*.svg=01;35:*.svgz=01;35:*.mng=01;35:*.pcx=01;35:*.mov=01;35:*.mpg=01;35:*.mpeg=01;35:*.m2v=01;35:*.mkv=01;35:*.webm=01;35:*.ogm=01;35:*.mp4=01;35:*.m4v=01;35:*.mp4v=01;35:*.vob=01;35:*.qt=01;35:*.nuv=01;35:*.wmv=01;35:*.asf=01;35:*.rm=01;35:*.rmvb=01;35:*.flc=01;35:*.avi=01;35:*.fli=01;35:*.flv=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:*.yuv=01;35:*.cgm=01;35:*.emf=01;35:*.axv=01;35:*.anx=01;35:*.ogv=01;35:*.ogx=01;35:*.aac=01;36:*.au=01;36:*.flac=01;36:*.mid=01;36:*.midi=01;36:*.mka=01;36:*.mp3=01;36:*.mpc=01;36:*.ogg=01;36:*.ra=01;36:*.wav=01;36:*.axa=01;36:*.oga=01;36:*.spx=01;36:*.xspf=01;36:
|
||||
TCL_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/qel
|
||||
HOSTTYPE=x86_64-linux
|
||||
OS_BITS=64bit
|
||||
HDLICE_HOME=/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86
|
||||
MAIL=/var/spool/mail/xuejin.wang
|
||||
PATH=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/../bin:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/inca/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools/cdsgcc/gcc/bin:/edatools/cadence/IXCOM/IXCOM23.03.005/bin:/edatools/cadence/WXE/WXE23.03.s005/share/vxe/gift/misc:/edatools/cadence/WXE/WXE23.03.s005/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/bin:/sbin
|
||||
XE_HARDWARE=z2
|
||||
PWD=/home/xuejin.wang/demo06/scrits
|
||||
_LMFILES_=/edatools/modules/WXE23.03.s005:/edatools/modules/IXCOM23.03.005:/edatools/modules/XCELIUM2309
|
||||
LANG=C
|
||||
MODULEPATH=/usr/share/Modules/modulefiles:/etc/modulefiles
|
||||
LOADEDMODULES=WXE23.03.s005:IXCOM23.03.005:XCELIUM2309
|
||||
DBOUT=./dbFiles
|
||||
LM_LICENSE_FILE=5280@172.16.10.96:5280@172.16.10.97:5280@172.16.10.95:5280@172.16.10.94
|
||||
KRB5CCNAME=KEYRING:persistent:1140202441
|
||||
QTHDLHOME=/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86
|
||||
SHLVL=1
|
||||
HOME=/home/xuejin.wang
|
||||
OSTYPE=linux
|
||||
XE_ROOT=/edatools/cadence/WXE/WXE23.03.s005
|
||||
VENDOR=unknown
|
||||
USERLIBPATH=/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools/systemc/lib/64bit/gnu:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/lib/64bit:/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86/lib/64bit:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/lib/64bit
|
||||
MACHTYPE=x86_64
|
||||
LOGNAME=xuejin.wang
|
||||
QTLIB=/usr/lib64/qt-3.3/lib
|
||||
SSH_CONNECTION=172.16.10.16 53482 172.16.10.128 22
|
||||
AXIS_ARCH=lib/x86-lx2-64
|
||||
MODULESHOME=/usr/share/Modules
|
||||
DBIN=.:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/lib/64bit:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin/64bit:./64bit:./dbFiles:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/et3:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin/x86-lx2-64:/et3mach
|
||||
LESSOPEN=||/usr/bin/lesspipe.sh %s
|
||||
XDG_RUNTIME_DIR=/run/user/1140202441
|
||||
DISPLAY=localhost:10.0
|
||||
HSV_ROOT=/edatools/cadence/WXE/WXE23.03.s005
|
||||
JE_MALLOC_CONF=dirty_decay_ms:10000,muzzy_decay_ms:5000,narenas:4
|
||||
CDNS_VRAPI_SEQ_DELTA_EN=1
|
||||
CDNS_VRAPI_INST_RELVL_EN=1
|
||||
CDNS_XBT_LOG_NAME=./tmp/xmsim-aidLogs_pid100527.log
|
||||
QTLOG_FILE=xe.msg
|
||||
CvAlEgAlRoOt=100527
|
||||
|
||||
@@ -0,0 +1,56 @@
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||||
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||||
## xeDebug starts at 09/22/2025 14:48:07 xuejin.wang V23.03.342.s005, HOST: scmp23, PID: 100527, DISPLAY: localhost:10.0
|
||||
xeDebug
|
||||
## 64bit program from /edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin on Linux 3.10.0-1160.el7.x86_64 64bit
|
||||
(c) 1991-2023 Cadence Design Systems, Inc. All rights reserved worldwide.
|
||||
See files in <rootdir>/share/vxe/install/Copyrights
|
||||
#)libdbg.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbk.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbs.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbserver.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvec.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvcp.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libcbid.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbgfv.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libswfv.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libinfinifile.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libcorun.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdrtl.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsdl.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsdltm.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libaba.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsst2w.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libfsdb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libfsdb_wrapper.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvw.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvcd.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtcf.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsaif.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsaifr.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libqtutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbgutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libeclutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libCompilerRT.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsmDB.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtypedb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libudqr.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libhdldb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libhdlucdb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libhwConfig.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdb3.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsideFile.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libmembin.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtcl.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtk.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtkdnd.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtix.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libfvenginei.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libzcompress.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libqt.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libqtutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libxeconfig.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsd.so - 23H1_WXE, V23.03.342.s005
|
||||
## xeDebug exits at 09/22/2025 14:48:15 Status: -1, PID: 100527
|
||||
## xeDebug Elapsed time: 0:00:08, CPU time: 0:00:00.02, Memory Usage: 1.3G
|
||||
## Child Proc. CPU time: 0:00:00.21
|
||||
+113
@@ -0,0 +1,113 @@
|
||||
|
||||
## xeDebug starts at 09/22/2025 14:48:07 xuejin.wang V23.03.342.s005, HOST: scmp23, PID: 100527, DISPLAY: localhost:10.0
|
||||
xeDebug
|
||||
## 64bit program from /edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin on Linux 3.10.0-1160.el7.x86_64 64bit
|
||||
(c) 1991-2023 Cadence Design Systems, Inc. All rights reserved worldwide.
|
||||
See files in <rootdir>/share/vxe/install/Copyrights
|
||||
#)libdbg.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbk.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbs.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbserver.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvec.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvcp.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libcbid.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbgfv.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libswfv.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libinfinifile.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libcorun.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdrtl.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsdl.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsdltm.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libaba.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsst2w.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libfsdb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libfsdb_wrapper.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvw.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libvcd.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtcf.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsaif.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsaifr.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libqtutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdbgutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libeclutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libCompilerRT.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsmDB.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtypedb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libudqr.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libhdldb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libhdlucdb.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libhwConfig.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libdb3.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsideFile.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libmembin.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtcl.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtk.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtkdnd.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libtix.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libfvenginei.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libzcompress.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libqt.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libqtutil.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libxeconfig.so - 23H1_WXE, V23.03.342.s005
|
||||
#)libsd.so - 23H1_WXE, V23.03.342.s005
|
||||
* System parameters:
|
||||
vm/overcommit_memory: 2
|
||||
vm/overcommit_ratio: 100
|
||||
vm/oom_dump_tasks: 1
|
||||
vm/oom_kill_allocating_task: 0
|
||||
% ulimit -a
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 13413065
|
||||
max locked memory (kbytes, -l) unlimited
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 16384
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) 32768
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 13413065
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
* CPU info:
|
||||
Number of CPUs: 144
|
||||
Name: Intel(R) Xeon(R) Gold 6240L CPU @ 2.60GHz
|
||||
Vendor: GenuineIntel, family: 6, model: 85, stepping: 7
|
||||
CPU min MHz: 1000.0000, BogoMIPS: 5200.00, virtualization: VT-x
|
||||
L1d cache: 32K, L1i cache: 32K, L2 cache: 1024K, L3 cache: 25344K
|
||||
* Memory info:
|
||||
total used free shared buffers cached
|
||||
Mem (GB): 3274 109 3165 0 0 7
|
||||
Swap (GB): 3 0 3
|
||||
* Load info:
|
||||
6490 threads
|
||||
Load (avg): 1 min (% CPU) | 5 min (% CPU) | 15 min (% CPU)
|
||||
0.04 ( 0% CPU) | 0.03 ( 0% CPU) | 0.05 ( 0% CPU)
|
||||
System info: scmp23 - xeDebug - 100527 363095 - qtInit - 2025-09-22 14:48:07 - 0.04 0% 0.03 0% 0.05 0% - 3274 109 3165 7 3 0 3
|
||||
000,000 s: WARNING (legacy-52177): There is no remote shell in your path.
|
||||
000,000 s: Check the value of XE_SECURE_CONNECTION and your OS environment.
|
||||
000,000 s: REPORT (legacy-55007): CDN_FV_NO_LOCAL_HOST value is auto. CDN_FV_NO_LOCAL_HOST setting is auto.
|
||||
000,000 s: XE> * Memory info:
|
||||
total used free shared buffers cached
|
||||
Mem (GB): 3274 109 3165 0 0 7
|
||||
Swap (GB): 3 0 3
|
||||
* Load info:
|
||||
6492 threads
|
||||
Load (avg): 1 min (% CPU) | 5 min (% CPU) | 15 min (% CPU)
|
||||
0.04 ( 0% CPU) | 0.03 ( 0% CPU) | 0.05 ( 0% CPU)
|
||||
System info: scmp23 - xeDebug - 100527 363095 - qtExit - 2025-09-22 14:48:15 - 0.04 0% 0.03 0% 0.05 0% - 3274 109 3165 7 3 0 3
|
||||
Peak usage info for xeDebug (pid 100527, ppid 363095) on scmp23: CPU usage 0.00, Peak mem (Res 0 GB, Virt 1 GB), freePhyMem 3166 GB, totalPhyMem 3275 GB, freeSwap 4 GB, totalSwap 4 GB
|
||||
source run_all.tcl
|
||||
000,008 s: INFO: Starting Palladium Z2 simulation...
|
||||
000,008 s: INFO: Loading design into Palladium Z2...
|
||||
000,008 s: ERROR: Failed to load design: invalid command name "load_design"
|
||||
000,008 s: xe> exit 1
|
||||
000,008 s: INFO (legacy-45111): Unhandled exception found: in make_fileptr(): No such file or directory. Exiting...
|
||||
DRM memory info: scmp23 - xeDebug - 100527 - 363095 - unknown unlimited
|
||||
## xeDebug exits at 09/22/2025 14:48:15 Status: -1, PID: 100527
|
||||
## xeDebug Elapsed time: 0:00:08, CPU time: 0:00:00.02, Memory Usage: 1.3G
|
||||
## Child Proc. CPU time: 0:00:00.21
|
||||
@@ -0,0 +1,47 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module testbench;
|
||||
// 1. 声明变量（限制位宽为 128 位，即 16 字符）
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
wire [31:0] pc_out;
|
||||
integer fd;
|
||||
reg [8*16:1] dump_path; // 16 字符足够存储路径
|
||||
|
||||
// 实例化被测设计
|
||||
top uut (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.pc_out(pc_out)
|
||||
);
|
||||
|
||||
// 2. 生成时钟
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
// 3. 波形生成和错误处理
|
||||
initial begin
|
||||
// 初始化路径（显式赋值）
|
||||
dump_path = "./wave.vcd"; // 自动填充低位，高位补零
|
||||
|
||||
// 尝试创建文件
|
||||
fd = $fopen(dump_path, "w");
|
||||
if (fd == 0) begin
|
||||
$display("ERROR: Cannot open %s for writing!", dump_path);
|
||||
$finish;
|
||||
end
|
||||
$fclose(fd);
|
||||
|
||||
// 初始化波形记录（添加 +access+r）
|
||||
$dumpfile(dump_path);
|
||||
$dumpvars(0, testbench); // 记录所有信号
|
||||
$display("Waveform will be saved to %s", dump_path);
|
||||
|
||||
// 复位和仿真控制
|
||||
reset_n = 0;
|
||||
#100 reset_n = 1;
|
||||
#10000 $finish;
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,46 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module testbench;
|
||||
// 1. 在模块开头声明所有变量
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
wire [31:0] pc_out;
|
||||
integer fd; // 文件描述符
|
||||
string dump_path = "/tmp/wave.vcd"; // 字符串变量
|
||||
|
||||
|
||||
// 实例化被测设计
|
||||
top uut (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.pc_out(pc_out)
|
||||
);
|
||||
|
||||
// 2. 生成时钟
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #5 clk = ~clk; // 100MHz 时钟
|
||||
end
|
||||
|
||||
// 3. 波形生成和错误处理
|
||||
initial begin
|
||||
// 尝试创建文件
|
||||
fd = $fopen(dump_path, "w");
|
||||
if (fd == 0) begin
|
||||
$display("ERROR: Cannot open %s for writing!", dump_path);
|
||||
$finish;
|
||||
end
|
||||
$fclose(fd);
|
||||
|
||||
// 初始化波形记录
|
||||
$dumpfile(dump_path);
|
||||
$dumpvars(0, testbench);
|
||||
$display("Waveform will be saved to %s", dump_path);
|
||||
|
||||
// 复位和仿真控制
|
||||
reset_n = 0;
|
||||
#100 reset_n = 1;
|
||||
#1000 $finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,49 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module testbench;
|
||||
// 1. 声明变量（纯 Verilog）
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
wire [31:0] pc_out;
|
||||
integer fd; // 文件描述符
|
||||
reg [8*80:1] dump_path; // 用 reg 数组模拟字符串
|
||||
|
||||
// 实例化被测设计
|
||||
top uut (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.pc_out(pc_out)
|
||||
);
|
||||
|
||||
// 2. 生成时钟
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #5 clk = ~clk; // 100MHz 时钟
|
||||
end
|
||||
|
||||
// 3. 波形生成和错误处理
|
||||
initial begin
|
||||
// 初始化路径（用字符串拼接模拟）
|
||||
dump_path = "/tmp/wave.vcd"; // Verilog 中直接赋值 reg 数组
|
||||
|
||||
// 尝试创建文件
|
||||
fd = $fopen(dump_path, "w");
|
||||
if (fd == 0) begin
|
||||
$display("ERROR: Cannot open ", dump_path, " for writing!"); // 字符串拼接
|
||||
$finish;
|
||||
end
|
||||
$fclose(fd);
|
||||
|
||||
// 初始化波形记录
|
||||
$dumpfile(dump_path);
|
||||
$dumpvars(0, testbench);
|
||||
$display("Waveform will be saved to ", dump_path); // 字符串拼接
|
||||
|
||||
// 复位和仿真控制
|
||||
reset_n = 0;
|
||||
#100 reset_n = 1;
|
||||
#1000 $finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,48 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module testbench;
|
||||
// 1. 声明变量（限制字符串位宽）
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
wire [31:0] pc_out;
|
||||
integer fd;
|
||||
reg [8*128:1] dump_path; // 限制为 128 字节（足够存储路径）
|
||||
|
||||
// 实例化被测设计
|
||||
top uut (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.pc_out(pc_out)
|
||||
);
|
||||
|
||||
// 2. 生成时钟
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
// 3. 波形生成和错误处理
|
||||
initial begin
|
||||
// 初始化路径（显式赋值）
|
||||
dump_path = "./wave.vcd";
|
||||
|
||||
// 尝试创建文件
|
||||
fd = $fopen(dump_path, "w");
|
||||
if (fd == 0) begin
|
||||
$display("ERROR: Cannot open %s for writing!", dump_path);
|
||||
$finish;
|
||||
end
|
||||
$fclose(fd);
|
||||
|
||||
// 初始化波形记录（添加 +access+r）
|
||||
$dumpfile(dump_path);
|
||||
$dumpvars(0, testbench); // 记录所有信号
|
||||
$display("Waveform will be saved to %s", dump_path);
|
||||
|
||||
// 复位和仿真控制
|
||||
reset_n = 0;
|
||||
#100 reset_n = 1;
|
||||
#1000 $finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,48 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module testbench;
|
||||
// 1. 声明变量（限制字符串位宽）
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
wire [31:0] pc_out;
|
||||
integer fd;
|
||||
reg [8*128:1] dump_path; // 限制为 128 字节（足够存储路径）
|
||||
|
||||
// 实例化被测设计
|
||||
top uut (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.pc_out(pc_out)
|
||||
);
|
||||
|
||||
// 2. 生成时钟
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
// 3. 波形生成和错误处理
|
||||
initial begin
|
||||
// 初始化路径（显式赋值）
|
||||
dump_path = "./wave.vcd";
|
||||
|
||||
// 尝试创建文件
|
||||
fd = $fopen(dump_path, "w");
|
||||
if (fd == 0) begin
|
||||
$display("ERROR: Cannot open %s for writing!", dump_path);
|
||||
$finish;
|
||||
end
|
||||
$fclose(fd);
|
||||
|
||||
// 初始化波形记录（添加 +access+r）
|
||||
$dumpfile(dump_path);
|
||||
$dumpvars(0, testbench); // 记录所有信号
|
||||
$display("Waveform will be saved to %s", dump_path);
|
||||
|
||||
// 复位和仿真控制
|
||||
reset_n = 0;
|
||||
#100 reset_n = 1;
|
||||
#1000 $finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,46 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module testbench;
|
||||
// 1. 声明所有变量
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
wire [31:0] pc_out;
|
||||
integer fd;
|
||||
string dump_path = "/tmp/wave.vcd"; // SystemVerilog 支持直接赋值
|
||||
|
||||
// 实例化被测设计
|
||||
top uut (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.pc_out(pc_out)
|
||||
);
|
||||
|
||||
// 2. 生成时钟
|
||||
initial begin
|
||||
clk = 0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
// 3. 波形生成和错误处理
|
||||
initial begin
|
||||
// 尝试创建文件
|
||||
fd = $fopen(dump_path, "w");
|
||||
if (fd == 0) begin
|
||||
string err_msg = $sformatf("ERROR: Cannot open %s for writing!", dump_path); // SystemVerilog 格式化
|
||||
$display("%s", err_msg);
|
||||
$finish;
|
||||
end
|
||||
$fclose(fd);
|
||||
|
||||
// 初始化波形记录
|
||||
$dumpfile(dump_path);
|
||||
$dumpvars(0, testbench);
|
||||
$display("Waveform will be saved to %s", dump_path); // 部分工具支持 %s
|
||||
|
||||
// 复位和仿真控制
|
||||
reset_n = 0;
|
||||
#100 reset_n = 1;
|
||||
#1000 $finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1 @@
|
||||
s1(22Sep2025:14:47:22): xmverilog +acc+rbn -64bit design/top.v testbench/testbench.v
|
||||
@@ -0,0 +1,10 @@
|
||||
xmverilog(64): 23.09-s001: (c) Copyright 1995-2023 Cadence Design Systems, Inc.
|
||||
TOOL: xmverilog 23.09-s001: Started on Sep 22, 2025 at 14:47:21 CST
|
||||
xmverilog
|
||||
+acc+rbn
|
||||
-64bit
|
||||
design/top.v
|
||||
testbench/testbench.v
|
||||
xmverilog: *E,FILEMIS: Cannot find the provided file design/top.v.
|
||||
xmverilog: *E,FILEMIS: Cannot find the provided file testbench/testbench.v.
|
||||
TOOL: xmverilog 23.09-s001: Exiting on Sep 22, 2025 at 14:47:22 CST (total: 00:00:01)
|
||||
Reference in New Issue
Block a user