Wang Xuejin f5bf2e30fc maste
2025-09-22 15:30:52 +08:00
2025-09-22 15:30:52 +08:00
2025-09-22 15:30:52 +08:00
2025-09-22 15:30:52 +08:00
2025-09-22 15:30:52 +08:00
2025-09-22 15:30:52 +08:00

RISC-V Demo for Palladium Z2

目录结构

riscv_demo/ ├── design/ │ └── top.v # RISC-V 顶层模块 ├── testbench/ │ └── testbench.v # 测试激励 └── scripts/ └── run_all.tcl # Palladium Z2 脚本

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Description
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Readme 132 KiB
Languages
Verilog 57.8%
Tcl 42.2%