From f5bf2e30fc6cbc19279817931b2c704e4582bc55 Mon Sep 17 00:00:00 2001 From: Wang Xuejin Date: Mon, 22 Sep 2025 15:30:52 +0800 Subject: [PATCH] maste --- README.md | 11 +- design/top.v | 13 + scrits/run_all.tcl | 41 + scrits/tmp/xeenv.log | 63 + scrits/tmp/xever.log | 56 + scrits/xe.msg | 113 + scrits/xeDebug.key | 0 scrits/xeDebug.log | 0 testbench/testbench.v | 47 + testbench/testbench.v01 | 46 + testbench/testbench.v02 | 49 + testbench/testbench.v03 | 48 + testbench/testbench.v04 | 48 + testbench/testbench.v_SystemVerilog | 46 + testbench/xmverilog.history | 1 + testbench/xmverilog.log | 10 + wave.vcd | 8097 +++++++++++++++++++++++++++ 17 files changed, 8688 insertions(+), 1 deletion(-) create mode 100644 design/top.v create mode 100644 scrits/run_all.tcl create mode 100644 scrits/tmp/xeenv.log create mode 100644 scrits/tmp/xever.log create mode 100644 scrits/xe.msg create mode 100644 scrits/xeDebug.key create mode 100644 scrits/xeDebug.log create mode 100644 testbench/testbench.v create mode 100644 testbench/testbench.v01 create mode 100644 testbench/testbench.v02 create mode 100644 testbench/testbench.v03 create mode 100644 testbench/testbench.v04 create mode 100644 testbench/testbench.v_SystemVerilog create mode 100644 testbench/xmverilog.history create mode 100644 testbench/xmverilog.log create mode 100644 wave.vcd diff --git a/README.md b/README.md index b16bf91..b1dffa8 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,11 @@ -# palladium_z2_demo +# RISC-V Demo for Palladium Z2 +## 目录结构 + +riscv_demo/ +├── design/ +│ └── top.v # RISC-V 顶层模块 +├── testbench/ +│ └── testbench.v # 测试激励 +└── scripts/ +└── run_all.tcl # Palladium Z2 脚本 diff --git a/design/top.v b/design/top.v new file mode 100644 index 0000000..ea2d1c8 --- /dev/null +++ b/design/top.v @@ -0,0 +1,13 @@ +`timescale 1ns/1ps +module top ( + input clk, + input reset_n, + output [31:0] pc_out +); + reg [31:0] pc; + always @(posedge clk or negedge reset_n) begin + if (!reset_n) pc <= 0; + else pc <= pc + 4; + end + assign pc_out = pc; +endmodule diff --git a/scrits/run_all.tcl b/scrits/run_all.tcl new file mode 100644 index 0000000..4f3e2c4 --- /dev/null +++ b/scrits/run_all.tcl @@ -0,0 +1,41 @@ +# run_all.tcl - Palladium Z2 Demo Script +puts "INFO: Starting Palladium Z2 simulation..." +set DESIGN_NAME "top" +set WORK_DIR "./work" +file mkdir $WORK_DIR +cd $WORK_DIR + +# 加载设计（示例，实际需替换为你的编译命令） +puts "INFO: Loading design into Palladium Z2..." +if {[catch {load_design -format verilog -top $DESIGN_NAME} err]} { + puts "ERROR: Failed to load design: $err" + exit 1 +} + +# 配置波形数据库 +puts "INFO: Setting up waveform database..." +database -open waves -shm +probe -create -all -depth all -database waves + +# 运行仿真 +puts "INFO: Running simulation for 1000 cycles..." +run 1000 + +# 调试信息 +if {[task_exists show_cpu_pc]} { + show_cpu_pc +} else { + puts "WARNING: show_cpu_pc task not found" +} + +# 保存波形 +if {[file exists waves.shm]} { + puts "INFO: Saving waveform traces..." + trace -name basic -database waves -add * + trace -save -database waves ./wave_debug.trn +} else { + puts "WARNING: No waveform database found" +} + +puts "INFO: Simulation completed successfully." +exit 0 diff --git a/scrits/tmp/xeenv.log b/scrits/tmp/xeenv.log new file mode 100644 index 0000000..b4a732e --- /dev/null +++ b/scrits/tmp/xeenv.log @@ -0,0 +1,63 @@ +## xeDebug starts at 09/22/2025 14:48:07, PID: 100527 +REMOTEHOST=172.16.10.16 +BLT_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/ui/blt +XDG_SESSION_ID=21345 +HOSTNAME=scmp23 +S3_ROOT=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin/64bit +HOST=scmp23 +TERM=xterm +SHELL=/bin/csh +AXIS_HOME=/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86 +SSH_CLIENT=172.16.10.16 53482 22 +QTHOME=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86 +TIX_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/ui/tix +TK_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/ui/tk +USERPATH=/edatools/cadence/XCELIUM/XCELIUM23.09.001/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/inca/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools/cdsgcc/gcc/bin:/edatools/cadence/IXCOM/IXCOM23.03.005/bin:/edatools/cadence/WXE/WXE23.03.s005/share/vxe/gift/misc:/edatools/cadence/WXE/WXE23.03.s005/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/usr/local/sbin:/usr/sbin +QTDIR=/usr/lib64/qt-3.3 +QTINC=/usr/lib64/qt-3.3/include +SSH_TTY=/dev/pts/0 +QT_GRAPHICSSYSTEM_CHECKED=1 +GROUP=domain users +USER=xuejin.wang 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+TCL_LIBRARY=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/qel +HOSTTYPE=x86_64-linux +OS_BITS=64bit +HDLICE_HOME=/edatools/cadence/IXCOM/IXCOM23.03.005/tools.lnx86 +MAIL=/var/spool/mail/xuejin.wang +PATH=/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/../bin:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools.lnx86/inca/bin:/edatools/cadence/XCELIUM/XCELIUM23.09.001/tools/cdsgcc/gcc/bin:/edatools/cadence/IXCOM/IXCOM23.03.005/bin:/edatools/cadence/WXE/WXE23.03.s005/share/vxe/gift/misc:/edatools/cadence/WXE/WXE23.03.s005/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/usr/local/sbin:/usr/sbin:/bin:/sbin +XE_HARDWARE=z2 +PWD=/home/xuejin.wang/demo06/scrits +_LMFILES_=/edatools/modules/WXE23.03.s005:/edatools/modules/IXCOM23.03.005:/edatools/modules/XCELIUM2309 +LANG=C +MODULEPATH=/usr/share/Modules/modulefiles:/etc/modulefiles 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+DBIN=.:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/lib/64bit:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin/64bit:./64bit:./dbFiles:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/etc/et3:/edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin/x86-lx2-64:/et3mach +LESSOPEN=||/usr/bin/lesspipe.sh %s +XDG_RUNTIME_DIR=/run/user/1140202441 +DISPLAY=localhost:10.0 +HSV_ROOT=/edatools/cadence/WXE/WXE23.03.s005 +JE_MALLOC_CONF=dirty_decay_ms:10000,muzzy_decay_ms:5000,narenas:4 +CDNS_VRAPI_SEQ_DELTA_EN=1 +CDNS_VRAPI_INST_RELVL_EN=1 +CDNS_XBT_LOG_NAME=./tmp/xmsim-aidLogs_pid100527.log +QTLOG_FILE=xe.msg +CvAlEgAlRoOt=100527 + diff --git a/scrits/tmp/xever.log b/scrits/tmp/xever.log new file mode 100644 index 0000000..e9b7a40 --- /dev/null +++ b/scrits/tmp/xever.log @@ -0,0 +1,56 @@ + +## xeDebug starts at 09/22/2025 14:48:07 xuejin.wang V23.03.342.s005, HOST: scmp23, PID: 100527, DISPLAY: localhost:10.0 +xeDebug +## 64bit program from /edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin on Linux 3.10.0-1160.el7.x86_64 64bit +(c) 1991-2023 Cadence Design Systems, Inc. All rights reserved worldwide. +See files in /share/vxe/install/Copyrights +#)libdbg.so - 23H1_WXE, V23.03.342.s005 +#)libdbk.so - 23H1_WXE, V23.03.342.s005 +#)libdbs.so - 23H1_WXE, V23.03.342.s005 +#)libdbserver.so - 23H1_WXE, V23.03.342.s005 +#)libvec.so - 23H1_WXE, V23.03.342.s005 +#)libvcp.so - 23H1_WXE, V23.03.342.s005 +#)libcbid.so - 23H1_WXE, V23.03.342.s005 +#)libdbgfv.so - 23H1_WXE, V23.03.342.s005 +#)libswfv.so - 23H1_WXE, V23.03.342.s005 +#)libinfinifile.so - 23H1_WXE, V23.03.342.s005 +#)libcorun.so - 23H1_WXE, V23.03.342.s005 +#)libdrtl.so - 23H1_WXE, V23.03.342.s005 +#)libsdl.so - 23H1_WXE, V23.03.342.s005 +#)libsdltm.so - 23H1_WXE, V23.03.342.s005 +#)libaba.so - 23H1_WXE, V23.03.342.s005 +#)libsst2w.so - 23H1_WXE, V23.03.342.s005 +#)libfsdb.so - 23H1_WXE, V23.03.342.s005 +#)libfsdb_wrapper.so - 23H1_WXE, V23.03.342.s005 +#)libvw.so - 23H1_WXE, V23.03.342.s005 +#)libvcd.so - 23H1_WXE, V23.03.342.s005 +#)libtcf.so - 23H1_WXE, V23.03.342.s005 +#)libsaif.so - 23H1_WXE, V23.03.342.s005 +#)libsaifr.so - 23H1_WXE, V23.03.342.s005 +#)libqtutil.so - 23H1_WXE, V23.03.342.s005 +#)libdbgutil.so - 23H1_WXE, V23.03.342.s005 +#)libeclutil.so - 23H1_WXE, V23.03.342.s005 +#)libCompilerRT.so - 23H1_WXE, V23.03.342.s005 +#)libdb.so - 23H1_WXE, V23.03.342.s005 +#)libsmDB.so - 23H1_WXE, V23.03.342.s005 +#)libtypedb.so - 23H1_WXE, V23.03.342.s005 +#)libudqr.so - 23H1_WXE, V23.03.342.s005 +#)libhdldb.so - 23H1_WXE, V23.03.342.s005 +#)libhdlucdb.so - 23H1_WXE, V23.03.342.s005 +#)libhwConfig.so - 23H1_WXE, V23.03.342.s005 +#)libdb3.so - 23H1_WXE, V23.03.342.s005 +#)libsideFile.so - 23H1_WXE, V23.03.342.s005 +#)libmembin.so - 23H1_WXE, V23.03.342.s005 +#)libtcl.so - 23H1_WXE, V23.03.342.s005 +#)libtk.so - 23H1_WXE, V23.03.342.s005 +#)libtkdnd.so - 23H1_WXE, V23.03.342.s005 +#)libtix.so - 23H1_WXE, V23.03.342.s005 +#)libfvenginei.so - 23H1_WXE, V23.03.342.s005 +#)libzcompress.so - 23H1_WXE, V23.03.342.s005 +#)libqt.so - 23H1_WXE, V23.03.342.s005 +#)libqtutil.so - 23H1_WXE, V23.03.342.s005 +#)libxeconfig.so - 23H1_WXE, V23.03.342.s005 +#)libsd.so - 23H1_WXE, V23.03.342.s005 +## xeDebug exits at 09/22/2025 14:48:15 Status: -1, PID: 100527 +## xeDebug Elapsed time: 0:00:08, CPU time: 0:00:00.02, Memory Usage: 1.3G +## Child Proc. CPU time: 0:00:00.21 diff --git a/scrits/xe.msg b/scrits/xe.msg new file mode 100644 index 0000000..87ceefc --- /dev/null +++ b/scrits/xe.msg @@ -0,0 +1,113 @@ + +## xeDebug starts at 09/22/2025 14:48:07 xuejin.wang V23.03.342.s005, HOST: scmp23, PID: 100527, DISPLAY: localhost:10.0 +xeDebug +## 64bit program from /edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin on Linux 3.10.0-1160.el7.x86_64 64bit +(c) 1991-2023 Cadence Design Systems, Inc. All rights reserved worldwide. +See files in /share/vxe/install/Copyrights +#)libdbg.so - 23H1_WXE, V23.03.342.s005 +#)libdbk.so - 23H1_WXE, V23.03.342.s005 +#)libdbs.so - 23H1_WXE, V23.03.342.s005 +#)libdbserver.so - 23H1_WXE, V23.03.342.s005 +#)libvec.so - 23H1_WXE, V23.03.342.s005 +#)libvcp.so - 23H1_WXE, V23.03.342.s005 +#)libcbid.so - 23H1_WXE, V23.03.342.s005 +#)libdbgfv.so - 23H1_WXE, V23.03.342.s005 +#)libswfv.so - 23H1_WXE, V23.03.342.s005 +#)libinfinifile.so - 23H1_WXE, V23.03.342.s005 +#)libcorun.so - 23H1_WXE, V23.03.342.s005 +#)libdrtl.so - 23H1_WXE, V23.03.342.s005 +#)libsdl.so - 23H1_WXE, V23.03.342.s005 +#)libsdltm.so - 23H1_WXE, V23.03.342.s005 +#)libaba.so - 23H1_WXE, V23.03.342.s005 +#)libsst2w.so - 23H1_WXE, V23.03.342.s005 +#)libfsdb.so - 23H1_WXE, V23.03.342.s005 +#)libfsdb_wrapper.so - 23H1_WXE, V23.03.342.s005 +#)libvw.so - 23H1_WXE, V23.03.342.s005 +#)libvcd.so - 23H1_WXE, V23.03.342.s005 +#)libtcf.so - 23H1_WXE, V23.03.342.s005 +#)libsaif.so - 23H1_WXE, V23.03.342.s005 +#)libsaifr.so - 23H1_WXE, V23.03.342.s005 +#)libqtutil.so - 23H1_WXE, V23.03.342.s005 +#)libdbgutil.so - 23H1_WXE, V23.03.342.s005 +#)libeclutil.so - 23H1_WXE, V23.03.342.s005 +#)libCompilerRT.so - 23H1_WXE, V23.03.342.s005 +#)libdb.so - 23H1_WXE, V23.03.342.s005 +#)libsmDB.so - 23H1_WXE, V23.03.342.s005 +#)libtypedb.so - 23H1_WXE, V23.03.342.s005 +#)libudqr.so - 23H1_WXE, V23.03.342.s005 +#)libhdldb.so - 23H1_WXE, V23.03.342.s005 +#)libhdlucdb.so - 23H1_WXE, V23.03.342.s005 +#)libhwConfig.so - 23H1_WXE, V23.03.342.s005 +#)libdb3.so - 23H1_WXE, V23.03.342.s005 +#)libsideFile.so - 23H1_WXE, V23.03.342.s005 +#)libmembin.so - 23H1_WXE, V23.03.342.s005 +#)libtcl.so - 23H1_WXE, V23.03.342.s005 +#)libtk.so - 23H1_WXE, V23.03.342.s005 +#)libtkdnd.so - 23H1_WXE, V23.03.342.s005 +#)libtix.so - 23H1_WXE, V23.03.342.s005 +#)libfvenginei.so - 23H1_WXE, V23.03.342.s005 +#)libzcompress.so - 23H1_WXE, V23.03.342.s005 +#)libqt.so - 23H1_WXE, V23.03.342.s005 +#)libqtutil.so - 23H1_WXE, V23.03.342.s005 +#)libxeconfig.so - 23H1_WXE, V23.03.342.s005 +#)libsd.so - 23H1_WXE, V23.03.342.s005 +* System parameters: +vm/overcommit_memory: 2 +vm/overcommit_ratio: 100 +vm/oom_dump_tasks: 1 +vm/oom_kill_allocating_task: 0 +% ulimit -a +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 13413065 +max locked memory (kbytes, -l) unlimited +max memory size (kbytes, -m) unlimited +open files (-n) 16384 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) 32768 +cpu time (seconds, -t) unlimited +max user processes (-u) 13413065 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited +* CPU info: + Number of CPUs: 144 + Name: Intel(R) Xeon(R) Gold 6240L CPU @ 2.60GHz + Vendor: GenuineIntel, family: 6, model: 85, stepping: 7 + CPU min MHz: 1000.0000, BogoMIPS: 5200.00, virtualization: VT-x + L1d cache: 32K, L1i cache: 32K, L2 cache: 1024K, L3 cache: 25344K +* Memory info: + total used free shared buffers cached +Mem (GB): 3274 109 3165 0 0 7 +Swap (GB): 3 0 3 +* Load info: + 6490 threads + Load (avg): 1 min (% CPU) | 5 min (% CPU) | 15 min (% CPU) + 0.04 ( 0% CPU) | 0.03 ( 0% CPU) | 0.05 ( 0% CPU) +System info: scmp23 - xeDebug - 100527 363095 - qtInit - 2025-09-22 14:48:07 - 0.04 0% 0.03 0% 0.05 0% - 3274 109 3165 7 3 0 3 +000,000 s: WARNING (legacy-52177): There is no remote shell in your path. +000,000 s: Check the value of XE_SECURE_CONNECTION and your OS environment. +000,000 s: REPORT (legacy-55007): CDN_FV_NO_LOCAL_HOST value is auto. CDN_FV_NO_LOCAL_HOST setting is auto. +000,000 s: XE> * Memory info: + total used free shared buffers cached +Mem (GB): 3274 109 3165 0 0 7 +Swap (GB): 3 0 3 +* Load info: + 6492 threads + Load (avg): 1 min (% CPU) | 5 min (% CPU) | 15 min (% CPU) + 0.04 ( 0% CPU) | 0.03 ( 0% CPU) | 0.05 ( 0% CPU) +System info: scmp23 - xeDebug - 100527 363095 - qtExit - 2025-09-22 14:48:15 - 0.04 0% 0.03 0% 0.05 0% - 3274 109 3165 7 3 0 3 +Peak usage info for xeDebug (pid 100527, ppid 363095) on scmp23: CPU usage 0.00, Peak mem (Res 0 GB, Virt 1 GB), freePhyMem 3166 GB, totalPhyMem 3275 GB, freeSwap 4 GB, totalSwap 4 GB +source run_all.tcl +000,008 s: INFO: Starting Palladium Z2 simulation... +000,008 s: INFO: Loading design into Palladium Z2... +000,008 s: ERROR: Failed to load design: invalid command name "load_design" +000,008 s: xe> exit 1 +000,008 s: INFO (legacy-45111): Unhandled exception found: in make_fileptr(): No such file or directory. Exiting... +DRM memory info: scmp23 - xeDebug - 100527 - 363095 - unknown unlimited +## xeDebug exits at 09/22/2025 14:48:15 Status: -1, PID: 100527 +## xeDebug Elapsed time: 0:00:08, CPU time: 0:00:00.02, Memory Usage: 1.3G +## Child Proc. CPU time: 0:00:00.21 diff --git a/scrits/xeDebug.key b/scrits/xeDebug.key new file mode 100644 index 0000000..e69de29 diff --git a/scrits/xeDebug.log b/scrits/xeDebug.log new file mode 100644 index 0000000..e69de29 diff --git a/testbench/testbench.v b/testbench/testbench.v new file mode 100644 index 0000000..3b81b84 --- /dev/null +++ b/testbench/testbench.v @@ -0,0 +1,47 @@ +`timescale 1ns/1ps + +module testbench; + // 1. 声明变量（限制位宽为 128 位，即 16 字符） + reg clk; + reg reset_n; + wire [31:0] pc_out; + integer fd; + reg [8*16:1] dump_path; // 16 字符足够存储路径 + + // 实例化被测设计 + top uut ( + .clk(clk), + .reset_n(reset_n), + .pc_out(pc_out) + ); + + // 2. 生成时钟 + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + // 3. 波形生成和错误处理 + initial begin + // 初始化路径（显式赋值） + dump_path = "./wave.vcd"; // 自动填充低位，高位补零 + + // 尝试创建文件 + fd = $fopen(dump_path, "w"); + if (fd == 0) begin + $display("ERROR: Cannot open %s for writing!", dump_path); + $finish; + end + $fclose(fd); + + // 初始化波形记录（添加 +access+r） + $dumpfile(dump_path); + $dumpvars(0, testbench); // 记录所有信号 + $display("Waveform will be saved to %s", dump_path); + + // 复位和仿真控制 + reset_n = 0; + #100 reset_n = 1; + #10000 $finish; + end +endmodule diff --git a/testbench/testbench.v01 b/testbench/testbench.v01 new file mode 100644 index 0000000..f8364f0 --- /dev/null +++ b/testbench/testbench.v01 @@ -0,0 +1,46 @@ +`timescale 1ns/1ps + +module testbench; + // 1. 在模块开头声明所有变量 + reg clk; + reg reset_n; + wire [31:0] pc_out; + integer fd; // 文件描述符 + string dump_path = "/tmp/wave.vcd"; // 字符串变量 + + +// 实例化被测设计 +top uut ( + .clk(clk), + .reset_n(reset_n), + .pc_out(pc_out) +); + +// 2. 生成时钟 +initial begin + clk = 0; + forever #5 clk = ~clk; // 100MHz 时钟 +end + +// 3. 波形生成和错误处理 +initial begin + // 尝试创建文件 + fd = $fopen(dump_path, "w"); + if (fd == 0) begin + $display("ERROR: Cannot open %s for writing!", dump_path); + $finish; + end + $fclose(fd); + + // 初始化波形记录 + $dumpfile(dump_path); + $dumpvars(0, testbench); + $display("Waveform will be saved to %s", dump_path); + + // 复位和仿真控制 + reset_n = 0; + #100 reset_n = 1; + #1000 $finish; +end + +endmodule diff --git a/testbench/testbench.v02 b/testbench/testbench.v02 new file mode 100644 index 0000000..a8bd561 --- /dev/null +++ b/testbench/testbench.v02 @@ -0,0 +1,49 @@ +`timescale 1ns/1ps + +module testbench; + // 1. 声明变量（纯 Verilog） + reg clk; + reg reset_n; + wire [31:0] pc_out; + integer fd; // 文件描述符 + reg [8*80:1] dump_path; // 用 reg 数组模拟字符串 + + // 实例化被测设计 + top uut ( + .clk(clk), + .reset_n(reset_n), + .pc_out(pc_out) + ); + + // 2. 生成时钟 + initial begin + clk = 0; + forever #5 clk = ~clk; // 100MHz 时钟 + end + + // 3. 波形生成和错误处理 + initial begin + // 初始化路径（用字符串拼接模拟） + dump_path = "/tmp/wave.vcd"; // Verilog 中直接赋值 reg 数组 + + // 尝试创建文件 + fd = $fopen(dump_path, "w"); + if (fd == 0) begin + $display("ERROR: Cannot open ", dump_path, " for writing!"); // 字符串拼接 + $finish; + end + $fclose(fd); + + // 初始化波形记录 + $dumpfile(dump_path); + $dumpvars(0, testbench); + $display("Waveform will be saved to ", dump_path); // 字符串拼接 + + // 复位和仿真控制 + reset_n = 0; + #100 reset_n = 1; + #1000 $finish; + end + +endmodule + diff --git a/testbench/testbench.v03 b/testbench/testbench.v03 new file mode 100644 index 0000000..4faac9f --- /dev/null +++ b/testbench/testbench.v03 @@ -0,0 +1,48 @@ +`timescale 1ns/1ps + +module testbench; + // 1. 声明变量（限制字符串位宽） + reg clk; + reg reset_n; + wire [31:0] pc_out; + integer fd; + reg [8*128:1] dump_path; // 限制为 128 字节（足够存储路径） + + // 实例化被测设计 + top uut ( + .clk(clk), + .reset_n(reset_n), + .pc_out(pc_out) + ); + + // 2. 生成时钟 + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + // 3. 波形生成和错误处理 + initial begin + // 初始化路径（显式赋值） + dump_path = "./wave.vcd"; + + // 尝试创建文件 + fd = $fopen(dump_path, "w"); + if (fd == 0) begin + $display("ERROR: Cannot open %s for writing!", dump_path); + $finish; + end + $fclose(fd); + + // 初始化波形记录（添加 +access+r） + $dumpfile(dump_path); + $dumpvars(0, testbench); // 记录所有信号 + $display("Waveform will be saved to %s", dump_path); + + // 复位和仿真控制 + reset_n = 0; + #100 reset_n = 1; + #1000 $finish; + end + +endmodule diff --git a/testbench/testbench.v04 b/testbench/testbench.v04 new file mode 100644 index 0000000..4faac9f --- /dev/null +++ b/testbench/testbench.v04 @@ -0,0 +1,48 @@ +`timescale 1ns/1ps + +module testbench; + // 1. 声明变量（限制字符串位宽） + reg clk; + reg reset_n; + wire [31:0] pc_out; + integer fd; + reg [8*128:1] dump_path; // 限制为 128 字节（足够存储路径） + + // 实例化被测设计 + top uut ( + .clk(clk), + .reset_n(reset_n), + .pc_out(pc_out) + ); + + // 2. 生成时钟 + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + // 3. 波形生成和错误处理 + initial begin + // 初始化路径（显式赋值） + dump_path = "./wave.vcd"; + + // 尝试创建文件 + fd = $fopen(dump_path, "w"); + if (fd == 0) begin + $display("ERROR: Cannot open %s for writing!", dump_path); + $finish; + end + $fclose(fd); + + // 初始化波形记录（添加 +access+r） + $dumpfile(dump_path); + $dumpvars(0, testbench); // 记录所有信号 + $display("Waveform will be saved to %s", dump_path); + + // 复位和仿真控制 + reset_n = 0; + #100 reset_n = 1; + #1000 $finish; + end + +endmodule diff --git a/testbench/testbench.v_SystemVerilog b/testbench/testbench.v_SystemVerilog new file mode 100644 index 0000000..41cc708 --- /dev/null +++ b/testbench/testbench.v_SystemVerilog @@ -0,0 +1,46 @@ +`timescale 1ns/1ps + +module testbench; + // 1. 声明所有变量 + reg clk; + reg reset_n; + wire [31:0] pc_out; + integer fd; + string dump_path = "/tmp/wave.vcd"; // SystemVerilog 支持直接赋值 + + // 实例化被测设计 + top uut ( + .clk(clk), + .reset_n(reset_n), + .pc_out(pc_out) + ); + + // 2. 生成时钟 + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + // 3. 波形生成和错误处理 + initial begin + // 尝试创建文件 + fd = $fopen(dump_path, "w"); + if (fd == 0) begin + string err_msg = $sformatf("ERROR: Cannot open %s for writing!", dump_path); // SystemVerilog 格式化 + $display("%s", err_msg); + $finish; + end + $fclose(fd); + + // 初始化波形记录 + $dumpfile(dump_path); + $dumpvars(0, testbench); + $display("Waveform will be saved to %s", dump_path); // 部分工具支持 %s + + // 复位和仿真控制 + reset_n = 0; + #100 reset_n = 1; + #1000 $finish; + end + +endmodule diff --git a/testbench/xmverilog.history b/testbench/xmverilog.history new file mode 100644 index 0000000..2a4bc7a --- /dev/null +++ b/testbench/xmverilog.history @@ -0,0 +1 @@ +s1(22Sep2025:14:47:22): xmverilog +acc+rbn -64bit design/top.v testbench/testbench.v diff --git a/testbench/xmverilog.log b/testbench/xmverilog.log new file mode 100644 index 0000000..9dcc1d2 --- /dev/null +++ b/testbench/xmverilog.log @@ -0,0 +1,10 @@ +xmverilog(64): 23.09-s001: (c) Copyright 1995-2023 Cadence Design Systems, Inc. +TOOL: xmverilog 23.09-s001: Started on Sep 22, 2025 at 14:47:21 CST +xmverilog + +acc+rbn + -64bit + design/top.v + testbench/testbench.v +xmverilog: *E,FILEMIS: Cannot find the provided file design/top.v. +xmverilog: *E,FILEMIS: Cannot find the provided file testbench/testbench.v. +TOOL: xmverilog 23.09-s001: Exiting on Sep 22, 2025 at 14:47:22 CST (total: 00:00:01) diff --git a/wave.vcd b/wave.vcd new file mode 100644 index 0000000..05f6a08 --- /dev/null +++ b/wave.vcd @@ -0,0 +1,8097 @@ +$date + Sep 22, 2025 15:17:58 +$end +$version + TOOL: xmsim(64) 23.09-s001 +$end +$timescale + 1 ps +$end + +$scope module testbench $end +$var reg 1 ! clk $end +$var reg 1 " reset_n $end +$var wire 32 # pc_out [31:0] $end +$var integer 32 $ fd $end +$var reg 128 % dump_path [128:1] $end + +$scope module uut $end +$var wire 1 & clk $end +$var wire 1 ' reset_n $end +$var wire 32 # pc_out [31:0] $end +$var reg 32 ( pc [31:0] $end +$upscope $end + +$upscope $end + +$enddefinitions $end +$dumpvars +0! +0" +b0 # +b10000000000000000000000000000011 $ +b101110001011110111011101100001011101100110010100101110011101100110001101100100 % +0& +0' +b0 ( +$end +#5000 +1! +1& +#10000 +0! +0& +#15000 +1! +1& +#20000 +0! +0& +#25000 +1! +1& +#30000 +0! +0& +#35000 +1! +1& +#40000 +0! +0& +#45000 +1! +1& +#50000 +0! +0& +#55000 +1! +1& +#60000 +0! +0& +#65000 +1! +1& +#70000 +0! +0& +#75000 +1! +1& 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