Wang Xuejin
47 rindas
1.1 KiB
Plaintext
47 rindas
1.1 KiB
Plaintext
`timescale 1ns/1ps
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module testbench;
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// 1. 声明所有变量
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reg clk;
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reg reset_n;
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wire [31:0] pc_out;
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integer fd;
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string dump_path = "/tmp/wave.vcd"; // SystemVerilog 支持直接赋值
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// 实例化被测设计
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top uut (
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.clk(clk),
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.reset_n(reset_n),
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.pc_out(pc_out)
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);
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// 2. 生成时钟
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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// 3. 波形生成和错误处理
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initial begin
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// 尝试创建文件
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fd = $fopen(dump_path, "w");
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if (fd == 0) begin
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string err_msg = $sformatf("ERROR: Cannot open %s for writing!", dump_path); // SystemVerilog 格式化
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$display("%s", err_msg);
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$finish;
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end
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$fclose(fd);
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// 初始化波形记录
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$dumpfile(dump_path);
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$dumpvars(0, testbench);
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$display("Waveform will be saved to %s", dump_path); // 部分工具支持 %s
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// 复位和仿真控制
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reset_n = 0;
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#100 reset_n = 1;
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#1000 $finish;
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end
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endmodule
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