maste

README.md

@@ -1,2 +1,11 @@
-# palladium_z2_demo
+# RISC-V Demo for Palladium Z2
 
+## 目录结构
+
+riscv_demo/
+├── design/
+│ └── top.v # RISC-V 顶层模块
+├── testbench/
+│ └── testbench.v # 测试激励
+└── scripts/
+└── run_all.tcl # Palladium Z2 脚本

design/top.v

@@ -0,0 +1,13 @@
+`timescale 1ns/1ps
+module top (
+    input clk,
+    input reset_n,
+    output [31:0] pc_out
+);
+    reg [31:0] pc;
+    always @(posedge clk or negedge reset_n) begin
+        if (!reset_n) pc <= 0;
+        else pc <= pc + 4;
+    end
+    assign pc_out = pc;
+endmodule

scrits/run_all.tcl

@@ -0,0 +1,41 @@
+# run_all.tcl - Palladium Z2 Demo Script
+puts "INFO: Starting Palladium Z2 simulation..."
+set DESIGN_NAME "top"
+set WORK_DIR "./work"
+file mkdir $WORK_DIR
+cd $WORK_DIR
+
+# 加载设计（示例，实际需替换为你的编译命令）
+puts "INFO: Loading design into Palladium Z2..."
+if {[catch {load_design -format verilog -top $DESIGN_NAME} err]} {
+    puts "ERROR: Failed to load design: $err"
+    exit 1
+}
+
+# 配置波形数据库
+puts "INFO: Setting up waveform database..."
+database -open waves -shm
+probe -create -all -depth all -database waves
+
+# 运行仿真
+puts "INFO: Running simulation for 1000 cycles..."
+run 1000
+
+# 调试信息
+if {[task_exists show_cpu_pc]} {
+    show_cpu_pc
+} else {
+    puts "WARNING: show_cpu_pc task not found"
+}
+
+# 保存波形
+if {[file exists waves.shm]} {
+    puts "INFO: Saving waveform traces..."
+    trace -name basic -database waves -add *
+    trace -save -database waves ./wave_debug.trn
+} else {
+    puts "WARNING: No waveform database found"
+}
+
+puts "INFO: Simulation completed successfully."
+exit 0

scrits/tmp/xeenv.log

@@ -0,0 +1,63 @@
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scrits/tmp/xever.log

@@ -0,0 +1,56 @@
+
+## xeDebug starts at 09/22/2025 14:48:07 xuejin.wang V23.03.342.s005, HOST: scmp23, PID: 100527, DISPLAY: localhost:10.0
+xeDebug
+## 64bit program from /edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin on Linux 3.10.0-1160.el7.x86_64 64bit
+(c) 1991-2023 Cadence Design Systems, Inc. All rights reserved worldwide.
+See files in <rootdir>/share/vxe/install/Copyrights
+#)libdbg.so - 23H1_WXE, V23.03.342.s005            
+#)libdbk.so - 23H1_WXE, V23.03.342.s005            
+#)libdbs.so - 23H1_WXE, V23.03.342.s005            
+#)libdbserver.so - 23H1_WXE, V23.03.342.s005            
+#)libvec.so - 23H1_WXE, V23.03.342.s005            
+#)libvcp.so - 23H1_WXE, V23.03.342.s005            
+#)libcbid.so - 23H1_WXE, V23.03.342.s005            
+#)libdbgfv.so - 23H1_WXE, V23.03.342.s005            
+#)libswfv.so - 23H1_WXE, V23.03.342.s005            
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+#)libcorun.so - 23H1_WXE, V23.03.342.s005            
+#)libdrtl.so - 23H1_WXE, V23.03.342.s005            
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+#)libsdltm.so - 23H1_WXE, V23.03.342.s005            
+#)libaba.so - 23H1_WXE, V23.03.342.s005            
+#)libsst2w.so - 23H1_WXE, V23.03.342.s005            
+#)libfsdb.so - 23H1_WXE, V23.03.342.s005            
+#)libfsdb_wrapper.so - 23H1_WXE, V23.03.342.s005            
+#)libvw.so - 23H1_WXE, V23.03.342.s005            
+#)libvcd.so - 23H1_WXE, V23.03.342.s005            
+#)libtcf.so - 23H1_WXE, V23.03.342.s005            
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+#)libdbgutil.so - 23H1_WXE, V23.03.342.s005            
+#)libeclutil.so - 23H1_WXE, V23.03.342.s005            
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+#)libsmDB.so - 23H1_WXE, V23.03.342.s005            
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+#)libudqr.so - 23H1_WXE, V23.03.342.s005            
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+#)libtkdnd.so - 23H1_WXE, V23.03.342.s005            
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+#)libqt.so - 23H1_WXE, V23.03.342.s005            
+#)libqtutil.so - 23H1_WXE, V23.03.342.s005            
+#)libxeconfig.so - 23H1_WXE, V23.03.342.s005            
+#)libsd.so - 23H1_WXE, V23.03.342.s005            
+## xeDebug exits at 09/22/2025 14:48:15 Status: -1, PID: 100527
+## xeDebug Elapsed time: 0:00:08, CPU time: 0:00:00.02, Memory Usage: 1.3G
+## Child Proc. CPU time: 0:00:00.21

scrits/xe.msg

@@ -0,0 +1,113 @@
+
+## xeDebug starts at 09/22/2025 14:48:07 xuejin.wang V23.03.342.s005, HOST: scmp23, PID: 100527, DISPLAY: localhost:10.0
+xeDebug
+## 64bit program from /edatools/cadence/WXE/WXE23.03.s005/tools.lnx86/bin on Linux 3.10.0-1160.el7.x86_64 64bit
+(c) 1991-2023 Cadence Design Systems, Inc. All rights reserved worldwide.
+See files in <rootdir>/share/vxe/install/Copyrights
+#)libdbg.so - 23H1_WXE, V23.03.342.s005            
+#)libdbk.so - 23H1_WXE, V23.03.342.s005            
+#)libdbs.so - 23H1_WXE, V23.03.342.s005            
+#)libdbserver.so - 23H1_WXE, V23.03.342.s005            
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+#)libvcp.so - 23H1_WXE, V23.03.342.s005            
+#)libcbid.so - 23H1_WXE, V23.03.342.s005            
+#)libdbgfv.so - 23H1_WXE, V23.03.342.s005            
+#)libswfv.so - 23H1_WXE, V23.03.342.s005            
+#)libinfinifile.so - 23H1_WXE, V23.03.342.s005            
+#)libcorun.so - 23H1_WXE, V23.03.342.s005            
+#)libdrtl.so - 23H1_WXE, V23.03.342.s005            
+#)libsdl.so - 23H1_WXE, V23.03.342.s005            
+#)libsdltm.so - 23H1_WXE, V23.03.342.s005            
+#)libaba.so - 23H1_WXE, V23.03.342.s005            
+#)libsst2w.so - 23H1_WXE, V23.03.342.s005            
+#)libfsdb.so - 23H1_WXE, V23.03.342.s005            
+#)libfsdb_wrapper.so - 23H1_WXE, V23.03.342.s005            
+#)libvw.so - 23H1_WXE, V23.03.342.s005            
+#)libvcd.so - 23H1_WXE, V23.03.342.s005            
+#)libtcf.so - 23H1_WXE, V23.03.342.s005            
+#)libsaif.so - 23H1_WXE, V23.03.342.s005            
+#)libsaifr.so - 23H1_WXE, V23.03.342.s005            
+#)libqtutil.so - 23H1_WXE, V23.03.342.s005            
+#)libdbgutil.so - 23H1_WXE, V23.03.342.s005            
+#)libeclutil.so - 23H1_WXE, V23.03.342.s005            
+#)libCompilerRT.so - 23H1_WXE, V23.03.342.s005            
+#)libdb.so - 23H1_WXE, V23.03.342.s005            
+#)libsmDB.so - 23H1_WXE, V23.03.342.s005            
+#)libtypedb.so - 23H1_WXE, V23.03.342.s005            
+#)libudqr.so - 23H1_WXE, V23.03.342.s005            
+#)libhdldb.so - 23H1_WXE, V23.03.342.s005            
+#)libhdlucdb.so - 23H1_WXE, V23.03.342.s005            
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+#)libsideFile.so - 23H1_WXE, V23.03.342.s005            
+#)libmembin.so - 23H1_WXE, V23.03.342.s005            
+#)libtcl.so - 23H1_WXE, V23.03.342.s005            
+#)libtk.so - 23H1_WXE, V23.03.342.s005            
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+#)libtix.so - 23H1_WXE, V23.03.342.s005            
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+#)libzcompress.so - 23H1_WXE, V23.03.342.s005            
+#)libqt.so - 23H1_WXE, V23.03.342.s005            
+#)libqtutil.so - 23H1_WXE, V23.03.342.s005            
+#)libxeconfig.so - 23H1_WXE, V23.03.342.s005            
+#)libsd.so - 23H1_WXE, V23.03.342.s005            
+* System parameters:
+vm/overcommit_memory: 2
+vm/overcommit_ratio: 100
+vm/oom_dump_tasks: 1
+vm/oom_kill_allocating_task: 0
+% ulimit -a
+core file size          (blocks, -c) 0
+data seg size           (kbytes, -d) unlimited
+scheduling priority             (-e) 0
+file size               (blocks, -f) unlimited
+pending signals                 (-i) 13413065
+max locked memory       (kbytes, -l) unlimited
+max memory size         (kbytes, -m) unlimited
+open files                      (-n) 16384
+pipe size            (512 bytes, -p) 8
+POSIX message queues     (bytes, -q) 819200
+real-time priority              (-r) 0
+stack size              (kbytes, -s) 32768
+cpu time               (seconds, -t) unlimited
+max user processes              (-u) 13413065
+virtual memory          (kbytes, -v) unlimited
+file locks                      (-x) unlimited
+* CPU info:
+  Number of CPUs: 144
+  Name: Intel(R) Xeon(R) Gold 6240L CPU @ 2.60GHz
+  Vendor: GenuineIntel, family: 6, model: 85, stepping: 7
+  CPU min MHz: 1000.0000, BogoMIPS: 5200.00, virtualization: VT-x
+  L1d cache: 32K, L1i cache: 32K, L2 cache: 1024K, L3 cache: 25344K
+* Memory info:
+              total     used     free   shared  buffers   cached
+Mem  (GB):     3274      109     3165        0        0        7
+Swap (GB):        3        0        3
+* Load info:
+  6490 threads
+  Load (avg):    1 min (% CPU) |     5 min (% CPU) |    15 min (% CPU)
+               0.04 (  0% CPU) |   0.03 (  0% CPU) |   0.05 (  0% CPU)
+System info: scmp23 - xeDebug - 100527 363095 - qtInit - 2025-09-22 14:48:07 - 0.04 0% 0.03 0% 0.05 0% - 3274 109 3165 7 3 0 3
+000,000 s: WARNING (legacy-52177): There is no remote shell in your path.
+000,000 s: Check the value of XE_SECURE_CONNECTION and your OS environment.
+000,000 s: REPORT (legacy-55007): CDN_FV_NO_LOCAL_HOST value is auto. CDN_FV_NO_LOCAL_HOST setting is auto.
+000,000 s: XE> * Memory info:
+              total     used     free   shared  buffers   cached
+Mem  (GB):     3274      109     3165        0        0        7
+Swap (GB):        3        0        3
+* Load info:
+  6492 threads
+  Load (avg):    1 min (% CPU) |     5 min (% CPU) |    15 min (% CPU)
+               0.04 (  0% CPU) |   0.03 (  0% CPU) |   0.05 (  0% CPU)
+System info: scmp23 - xeDebug - 100527 363095 - qtExit - 2025-09-22 14:48:15 - 0.04 0% 0.03 0% 0.05 0% - 3274 109 3165 7 3 0 3
+Peak usage info for xeDebug (pid 100527, ppid 363095) on scmp23: CPU usage 0.00, Peak mem (Res 0 GB, Virt 1 GB), freePhyMem 3166 GB, totalPhyMem 3275 GB, freeSwap 4 GB, totalSwap 4 GB
+source run_all.tcl
+000,008 s: INFO: Starting Palladium Z2 simulation...
+000,008 s: INFO: Loading design into Palladium Z2...
+000,008 s: ERROR: Failed to load design: invalid command name "load_design"
+000,008 s: xe> exit 1
+000,008 s: INFO (legacy-45111): Unhandled exception found: in make_fileptr(): No such file or directory. Exiting...
+DRM memory info: scmp23 - xeDebug - 100527 - 363095 - unknown unlimited
+## xeDebug exits at 09/22/2025 14:48:15 Status: -1, PID: 100527
+## xeDebug Elapsed time: 0:00:08, CPU time: 0:00:00.02, Memory Usage: 1.3G
+## Child Proc. CPU time: 0:00:00.21

testbench/testbench.v

@@ -0,0 +1,47 @@
+`timescale 1ns/1ps
+
+module testbench;
+    // 1. 声明变量（限制位宽为 128 位，即 16 字符）
+    reg clk;
+    reg reset_n;
+    wire [31:0] pc_out;
+    integer fd;
+    reg [8*16:1] dump_path;  // 16 字符足够存储路径
+
+    // 实例化被测设计
+    top uut (
+        .clk(clk),
+        .reset_n(reset_n),
+        .pc_out(pc_out)
+    );
+
+    // 2. 生成时钟
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;
+    end
+
+    // 3. 波形生成和错误处理
+    initial begin
+        // 初始化路径（显式赋值）
+        dump_path = "./wave.vcd";  // 自动填充低位，高位补零
+
+        // 尝试创建文件
+        fd = $fopen(dump_path, "w");
+        if (fd == 0) begin
+            $display("ERROR: Cannot open %s for writing!", dump_path);
+            $finish;
+        end
+        $fclose(fd);
+
+        // 初始化波形记录（添加 +access+r）
+        $dumpfile(dump_path);
+        $dumpvars(0, testbench);  // 记录所有信号
+        $display("Waveform will be saved to %s", dump_path);
+
+        // 复位和仿真控制
+        reset_n = 0;
+        #100 reset_n = 1;
+        #10000 $finish;
+    end
+endmodule

testbench/testbench.v01

@@ -0,0 +1,46 @@
+`timescale 1ns/1ps
+
+module testbench;
+    // 1. 在模块开头声明所有变量
+    reg clk;
+    reg reset_n;
+    wire [31:0] pc_out;
+    integer fd;  // 文件描述符
+    string dump_path = "/tmp/wave.vcd";  // 字符串变量
+
+
+// 实例化被测设计
+top uut (
+    .clk(clk),
+    .reset_n(reset_n),
+    .pc_out(pc_out)
+);
+
+// 2. 生成时钟
+initial begin
+    clk = 0;
+    forever #5 clk = ~clk;  // 100MHz 时钟
+end
+
+// 3. 波形生成和错误处理
+initial begin
+    // 尝试创建文件
+    fd = $fopen(dump_path, "w");
+    if (fd == 0) begin
+        $display("ERROR: Cannot open %s for writing!", dump_path);
+        $finish;
+    end
+    $fclose(fd);
+
+    // 初始化波形记录
+    $dumpfile(dump_path);
+    $dumpvars(0, testbench);
+    $display("Waveform will be saved to %s", dump_path);
+
+    // 复位和仿真控制
+    reset_n = 0;
+    #100 reset_n = 1;
+    #1000 $finish;
+end
+
+endmodule

testbench/testbench.v02

@@ -0,0 +1,49 @@
+`timescale 1ns/1ps
+
+module testbench;
+    // 1. 声明变量（纯 Verilog）
+    reg clk;
+    reg reset_n;
+    wire [31:0] pc_out;
+    integer fd;  // 文件描述符
+    reg [8*80:1] dump_path;  // 用 reg 数组模拟字符串
+
+    // 实例化被测设计
+    top uut (
+        .clk(clk),
+        .reset_n(reset_n),
+        .pc_out(pc_out)
+    );
+
+    // 2. 生成时钟
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;  // 100MHz 时钟
+    end
+
+    // 3. 波形生成和错误处理
+    initial begin
+        // 初始化路径（用字符串拼接模拟）
+        dump_path = "/tmp/wave.vcd";  // Verilog 中直接赋值 reg 数组
+
+        // 尝试创建文件
+        fd = $fopen(dump_path, "w");
+        if (fd == 0) begin
+            $display("ERROR: Cannot open ", dump_path, " for writing!");  // 字符串拼接
+            $finish;
+        end
+        $fclose(fd);
+
+        // 初始化波形记录
+        $dumpfile(dump_path);
+        $dumpvars(0, testbench);
+        $display("Waveform will be saved to ", dump_path);  // 字符串拼接
+
+        // 复位和仿真控制
+        reset_n = 0;
+        #100 reset_n = 1;
+        #1000 $finish;
+    end
+
+endmodule
+

testbench/testbench.v03

@@ -0,0 +1,48 @@
+`timescale 1ns/1ps
+
+module testbench;
+    // 1. 声明变量（限制字符串位宽）
+    reg clk;
+    reg reset_n;
+    wire [31:0] pc_out;
+    integer fd;
+    reg [8*128:1] dump_path;  // 限制为 128 字节（足够存储路径）
+
+    // 实例化被测设计
+    top uut (
+        .clk(clk),
+        .reset_n(reset_n),
+        .pc_out(pc_out)
+    );
+
+    // 2. 生成时钟
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;
+    end
+
+    // 3. 波形生成和错误处理
+    initial begin
+        // 初始化路径（显式赋值）
+        dump_path = "./wave.vcd";
+
+        // 尝试创建文件
+        fd = $fopen(dump_path, "w");
+        if (fd == 0) begin
+            $display("ERROR: Cannot open %s for writing!", dump_path);
+            $finish;
+        end
+        $fclose(fd);
+
+        // 初始化波形记录（添加 +access+r）
+        $dumpfile(dump_path);
+        $dumpvars(0, testbench);  // 记录所有信号
+        $display("Waveform will be saved to %s", dump_path);
+
+        // 复位和仿真控制
+        reset_n = 0;
+        #100 reset_n = 1;
+        #1000 $finish;
+    end
+
+endmodule

testbench/testbench.v04

@@ -0,0 +1,48 @@
+`timescale 1ns/1ps
+
+module testbench;
+    // 1. 声明变量（限制字符串位宽）
+    reg clk;
+    reg reset_n;
+    wire [31:0] pc_out;
+    integer fd;
+    reg [8*128:1] dump_path;  // 限制为 128 字节（足够存储路径）
+
+    // 实例化被测设计
+    top uut (
+        .clk(clk),
+        .reset_n(reset_n),
+        .pc_out(pc_out)
+    );
+
+    // 2. 生成时钟
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;
+    end
+
+    // 3. 波形生成和错误处理
+    initial begin
+        // 初始化路径（显式赋值）
+        dump_path = "./wave.vcd";
+
+        // 尝试创建文件
+        fd = $fopen(dump_path, "w");
+        if (fd == 0) begin
+            $display("ERROR: Cannot open %s for writing!", dump_path);
+            $finish;
+        end
+        $fclose(fd);
+
+        // 初始化波形记录（添加 +access+r）
+        $dumpfile(dump_path);
+        $dumpvars(0, testbench);  // 记录所有信号
+        $display("Waveform will be saved to %s", dump_path);
+
+        // 复位和仿真控制
+        reset_n = 0;
+        #100 reset_n = 1;
+        #1000 $finish;
+    end
+
+endmodule

testbench/testbench.v_SystemVerilog

@@ -0,0 +1,46 @@
+`timescale 1ns/1ps
+
+module testbench;
+    // 1. 声明所有变量
+    reg clk;
+    reg reset_n;
+    wire [31:0] pc_out;
+    integer fd;
+    string dump_path = "/tmp/wave.vcd";  // SystemVerilog 支持直接赋值
+
+    // 实例化被测设计
+    top uut (
+        .clk(clk),
+        .reset_n(reset_n),
+        .pc_out(pc_out)
+    );
+
+    // 2. 生成时钟
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;
+    end
+
+    // 3. 波形生成和错误处理
+    initial begin
+        // 尝试创建文件
+        fd = $fopen(dump_path, "w");
+        if (fd == 0) begin
+            string err_msg = $sformatf("ERROR: Cannot open %s for writing!", dump_path);  // SystemVerilog 格式化
+            $display("%s", err_msg);
+            $finish;
+        end
+        $fclose(fd);
+
+        // 初始化波形记录
+        $dumpfile(dump_path);
+        $dumpvars(0, testbench);
+        $display("Waveform will be saved to %s", dump_path);  // 部分工具支持 %s
+
+        // 复位和仿真控制
+        reset_n = 0;
+        #100 reset_n = 1;
+        #1000 $finish;
+    end
+
+endmodule

testbench/xmverilog.history

@@ -0,0 +1 @@
+s1(22Sep2025:14:47:22):  xmverilog +acc+rbn -64bit design/top.v testbench/testbench.v 

testbench/xmverilog.log

@@ -0,0 +1,10 @@
+xmverilog(64): 23.09-s001: (c) Copyright 1995-2023 Cadence Design Systems, Inc.
+TOOL:	xmverilog	23.09-s001: Started on Sep 22, 2025 at 14:47:21 CST
+xmverilog
+	+acc+rbn
+	-64bit
+	design/top.v
+	testbench/testbench.v
+xmverilog: *E,FILEMIS: Cannot find the provided file design/top.v.
+xmverilog: *E,FILEMIS: Cannot find the provided file testbench/testbench.v.
+TOOL:	xmverilog	23.09-s001: Exiting on Sep 22, 2025 at 14:47:22 CST  (total: 00:00:01)

wave.vcd

@@ -0,0 +1,8097 @@
+$date
+    Sep 22, 2025  15:17:58
+$end
+$version
+    TOOL:	xmsim(64)	23.09-s001
+$end
+$timescale
+    1 ps
+$end
+
+$scope module testbench $end
+$var reg       1 !    clk $end
+$var reg       1 "    reset_n $end
+$var wire     32 #    pc_out [31:0] $end
+$var integer  32 $    fd $end
+$var reg      128 %    dump_path [128:1] $end
+
+$scope module uut $end
+$var wire      1 &    clk  $end
+$var wire      1 '    reset_n  $end
+$var wire     32 #    pc_out [31:0] $end
+$var reg      32 (    pc [31:0] $end
+$upscope $end
+
+$upscope $end
+
+$enddefinitions $end
+$dumpvars
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