Wang Xuejin
14 行
264 B
Verilog
14 行
264 B
Verilog
`timescale 1ns/1ps
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module top (
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input clk,
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input reset_n,
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output [31:0] pc_out
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);
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reg [31:0] pc;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) pc <= 0;
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else pc <= pc + 4;
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end
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assign pc_out = pc;
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endmodule
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