maste

design/top.v

@@ -0,0 +1,13 @@
+`timescale 1ns/1ps
+module top (
+    input clk,
+    input reset_n,
+    output [31:0] pc_out
+);
+    reg [31:0] pc;
+    always @(posedge clk or negedge reset_n) begin
+        if (!reset_n) pc <= 0;
+        else pc <= pc + 4;
+    end
+    assign pc_out = pc;
+endmodule