Wang Xuejin
11 lines
443 B
Plaintext
11 lines
443 B
Plaintext
xmverilog(64): 23.09-s001: (c) Copyright 1995-2023 Cadence Design Systems, Inc.
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TOOL: xmverilog 23.09-s001: Started on Sep 22, 2025 at 14:47:21 CST
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xmverilog
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+acc+rbn
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-64bit
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design/top.v
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testbench/testbench.v
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xmverilog: *E,FILEMIS: Cannot find the provided file design/top.v.
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xmverilog: *E,FILEMIS: Cannot find the provided file testbench/testbench.v.
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TOOL: xmverilog 23.09-s001: Exiting on Sep 22, 2025 at 14:47:22 CST (total: 00:00:01)
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