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Wang Xuejin f5bf2e30fc maste
2025-09-22 15:30:52 +08:00

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xmverilog(64): 23.09-s001: (c) Copyright 1995-2023 Cadence Design Systems, Inc.
TOOL: xmverilog 23.09-s001: Started on Sep 22, 2025 at 14:47:21 CST
xmverilog
+acc+rbn
-64bit
design/top.v
testbench/testbench.v
xmverilog: *E,FILEMIS: Cannot find the provided file design/top.v.
xmverilog: *E,FILEMIS: Cannot find the provided file testbench/testbench.v.
TOOL: xmverilog 23.09-s001: Exiting on Sep 22, 2025 at 14:47:22 CST (total: 00:00:01)