Wang Xuejin
42 行
1.0 KiB
Tcl
42 行
1.0 KiB
Tcl
# run_all.tcl - Palladium Z2 Demo Script
|
|
puts "INFO: Starting Palladium Z2 simulation..."
|
|
set DESIGN_NAME "top"
|
|
set WORK_DIR "./work"
|
|
file mkdir $WORK_DIR
|
|
cd $WORK_DIR
|
|
|
|
# 加载设计（示例，实际需替换为你的编译命令）
|
|
puts "INFO: Loading design into Palladium Z2..."
|
|
if {[catch {load_design -format verilog -top $DESIGN_NAME} err]} {
|
|
puts "ERROR: Failed to load design: $err"
|
|
exit 1
|
|
}
|
|
|
|
# 配置波形数据库
|
|
puts "INFO: Setting up waveform database..."
|
|
database -open waves -shm
|
|
probe -create -all -depth all -database waves
|
|
|
|
# 运行仿真
|
|
puts "INFO: Running simulation for 1000 cycles..."
|
|
run 1000
|
|
|
|
# 调试信息
|
|
if {[task_exists show_cpu_pc]} {
|
|
show_cpu_pc
|
|
} else {
|
|
puts "WARNING: show_cpu_pc task not found"
|
|
}
|
|
|
|
# 保存波形
|
|
if {[file exists waves.shm]} {
|
|
puts "INFO: Saving waveform traces..."
|
|
trace -name basic -database waves -add *
|
|
trace -save -database waves ./wave_debug.trn
|
|
} else {
|
|
puts "WARNING: No waveform database found"
|
|
}
|
|
|
|
puts "INFO: Simulation completed successfully."
|
|
exit 0
|